It is expected H.265 can obtain the same quality as H.264 at half the bit rate. Cisco published a demo at Youtube to show the H.265 capability of high quality video with great bandwidth. Moreover, H,265 can cover both scenarios and support a wide range of applications, from DTH transmission to acquisition and storage.
According to Cisco's latest Global Mobile Data Traffic Forecast, world mobile data traffic to explode by factor of 26 by 2015, and two-thirds of the world's mobile data traffic will be video by 2015.
The technical architecture of HEVC is basically conceptually similar to H.264 (and
prior standards):
- Block-based
- Variable block sizes
- Block motion compensation
- Fractional-pel motion vectors
- Spatial intra prediction
- Spatial transform of residual difference
- Integer-based transform designs
- Arithmetic or VLC-based entropy coding
- In-loop filtering to form final decoded picture
Lots of variations at the individual “tool” level include:
- Coding unit tree structure (8x8 up to 64x64 luma samples)
- Prediction units (N=4, 8, 16, 32, shapes: 2Nx2N, NxN for smallest; for inter also 2NxN & Nx2N)
- Transforms can cross prediction unit boundaries for Intra; not for Inter
- Transform unit tree structure (maximum of 3 levels) Transform unit tree structure (maximum of 2 levels)
- Transform block size of 4x4 to 32x32 samples (always square)
- Angular intra prediction (17 directions for 4x4, 3 directions for 64x64, 34 directions for others)
- Luma motion compensation: 1/4 sample precision, 8x8 separable with 6 bit tap values
- Chroma motion compensation: 1/8 sample precision, 4x4 separable with 6 bit tap values
- Advanced motion vector prediction with motion vector “competition” and “merging”
The following table shows the H.265 tool set and compares with H.264:
| AVC High profile | HEVC High efficiency | HEVC Low complexity |
|---|---|---|
| 16 × 16 macroblock | Coding unit quadtree structure (64 × 64 down to 8 × 8) | |
| Partitions down to 4 × 4 | Prediction units (64 × 64 down to 4 × 4, square intra/inter + non-square inter) | |
| 8 × 8 and 4 × 4 transforms | Transforms unites (32 × 32, 16 × 16, 8 × 8, 4 × 4 intra/inter + non-square inter) | |
| Intra prediction (9 directions) | Intra prediction (17 directions for 4 × 4, 3 directions for 16 × 16, 34 directions for rest) | |
| Inter prediction luma 6-tap + 2-tap to 1/4 pel | Inter prediction luma 8-tap to 1/4 pel | |
| Inter prediction chroma bi-linear interpolation | Inter prediction chroma 4-tap to 1/8 pel | |
| Motion vector prediction | Advanced motion vector prediction (spatial + temporal) | |
| CABAC or CAVLC | CABAC (Context Adaptive Binary Arithmetic Docing) | CAVLC (Context Adaptive Variabl Length Coding) |
| 8b/sample storage and output | 10b/sample storage and output | 8b/sample storage and output |
| Deblocking filter | Deblocking filter | |
| - | Adaptive Loop Filter (AFL) and Sample Adaptive Offset (SAO) filter | Sample Adaptive Offset (SAO) filter |
Table 1. The toolsets provided to implement HEVC encoders can be used and modified to improve bit rate, video quality or both. Information courtesy Matthew Goldman, Ericsson, from the paper “High Efficiency Video Coding (HEVC) - The Next Generation Compression Technology,” presented at the SMPTE 2011 Technical Conference and Exhibition, Oct. 25-27, 2011.
Since technologies move so quickly, it makes it nearly impossible for broadcast engineers and designers working to get ahead of the competition to rely on application specific standard products (ASSPs) as the backbone of their hardware solutions. For this reason, Xilinx ROBERT GREEN AND AARON BEHMAN believed that FPGAs offer the only viable platform for the next several years for companies hoping to exploit advantages of HEVC, since FPGAs can support the HEVC standard in software with hardware acceleration blocks for motion estimation and CABAC/CAVLC, which enables tradeoffs in device resource and performance while promoting design productivity. They said, "Depending on the application, the ability to trade off computational complexity, compression rate, robustness of errors and processing delay time are all elements that can only be evaluated in real-time with an FPGA-based design."
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