Post-Synthesis Simulation Using Synplify, NC-verilog and ISE

A FPGA synthesis tool such as Synplify optimizes the design code and converts it from RTL to a post-synthesis netlist. A netlist can be

File Type	Description
.edf	Netlist for Place & Route tools
.vhm	Synthesized netlist for simulation
.vm	Synthesized netlist for simulation
.ucf	Constraints for P&R tools

For Xilinx FPGA, we may use NC-Verilog to do a post-synthesis simulation with the ISE libraries including unisims or simprim and glpl.v. For example, a script may like

ncverilog -sv -y ${XILINX}/verilog /unisims +incdir+${XILINX}/verilog/src +libext+.v ${XILINX}/verilog/src/glbl.v test.vm -f vm.f +nctop:test -w -timescale 1ns/1ns

The vm.f includes other simulation Verilog files. -sv is for system Verilog. test is the top module of Synplify synthesis.

The following links also provide good information using NC-Verilog tools for post-synthesis simulation:

http://intranet.daiict.ac.in/~vlsi/Netlist_Simulate.pdf

http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/techdocs/5474.htm

http://www.xilinx.com/itp/xilinx6/books/docs/sim/sim.pdf

http://www.cse.psu.edu/~eachempa/CSE478/cg478_2005/slides/synthesis.pdf

The following link shows a Conformal FPGA and Synplify Pro Flow

http://www.xilinx.com/itp/xilinx6/books/data/docs/sim/sim0077_10.html#wp263612