Tuesday, March 31, 2009

FPGA projects dominate ASIC by a 30 to 1 margin




EE Times 

SAN FRANCISCO—FPGAs are displacing ASICs—a trend that in 2009 will be exacerbated by the global financial crisis—and now have a 30-to-one edge in design starts, according to market research firm Gartner Inc.

ASIC design starts are expected to drop by 22 percent in 2009 as the economy causes firms to push out and—in some cases—cancel designs, Gartner (Stamford, Conn.) said.

ASIC design starts—completed designs that have taped out—fell 9.5 percent in 2008, according to Gartner. The firm said the financial crisis started to take its toll on ASIC design starts in the fourth quarter of 2008 in the form of push-outs of design projects into 2009.

Since most ASIC vendors have a design cancel fee, there will likely be no word of them being canceled, Gartner said. But just how many of these designs will never go forward is a key question, the firm said.

"More likely, we will see a large percentage of these questionable designs not hit any production and die a slow death by indefinite push-outs," wrote Gartner analyst Bryan Lewis in a report dated Monday (March 30).

New ASIC design starts have been dropping in numbers for years due to system integration, rising design costs, and other types of devices, such as FPGAs or application-specific standard products, taking the socket, Gartner said.

At a product launch event in February, Xilinx Inc. president and CEO Moshe Gavrielov presented data on the trend of declining ASIC starts. Gavrielov spoke of a "programmable imperative," when, he said, FPGAs will dominate for many applications while traditional gate arrays and structured arrays are relegated to high-volume tasks.

Gavrielov argued that factors such as the technological evolution of the FPGA and economic factors such as the rising cost of photomasks make FPGAs the attractive choice for all but the most high-volume applications.

Thursday, March 26, 2009

On2 readies 1080p video encoding for mobiles

http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=214201627


EE Times Europe View Blog


BARCELONA, Spain — Silicon IP specialist for digital video, On2 Technologies, is using this week's Mobile Word Congress here to launch its hard-wired HD video encoder that supports full-frame 1080p video.

Dubbed the Hantro 8270, the part lets mobile phone designers add the latest video decoding capabilities, including H.264 Baseline, Main and High Profile video along with 16Mpixel JPEG still images.

The encoder has a minimal clock frequency requirement, less than 250MHz needed for 30fps 1080p video.

Jani Huoponen, VP of product marketing at On2, said the Hantro 8270 "takes video encoding to the next level," and that the company "is talking to several SoC suppliers targeting high end smartphones who want to design in and license the IP for next generation devices."

Previous generation decoders from On2's Hantro division, such as the 8190launched at last year's MWC, are already being designed into devices for mobile applications.

Huoponen would not reveal the names of customers for the latest design, but said companies such as Freescale Semiconductors, MediaTek and Infineon Technologies are major customers of its IP for both mobile applications and for VP6 and VP7 video compression for desktops.

On2 acquired Oulu, Finland-based video compression technology specialist Hantro Oy in late 2007.

On2's codec portfolio includes TrueMotion V6 and V7, MPEG2 and 4, VC-1, H2.64. The proprietary TrueMotion codecs are used in Adobe Flash and Skype, amongst others.

The 8270 is being offered first for FPGAs and Huoponen said he expects first silicon to be in production during the first half of 2010. He said the 8270 IP will be available for licensing from next month and expects the first applications will be for high end phones and the video surveillance / security market.

"The biggest opportunity for us will definitely be mobile phones as ours is a licensing model, and that is where the volumes will be."

Power consumption has been a critical design issue for 1080p capable decoders targeting the mobiles sector, as well as maintaining a low overall clock frequency, said Huoponen. He adds On2 has focused on efficient pipeline utilization and smart parallelism for key functions to meet the industry's expectations for 1080p video.

Huoponen considers U.K group Imagination Technologies and Korean company Chips and Media as the main competition for hard-wired IP, but he stresses they mostly target consumer applications, not the mobile phones sector.


Hantro 8270 H.264 Video Encoder 

Configurable hardware (RTL) design for low powered multimedia SOCs

Ultra low power high performance 1080p H.264 encoder IP core
The Hantro 8270 H.264 encoder core processes up to 1920 x 1080 resolution video at 30 frames per second. Designed for any HD application, from mobile devices to security cameras, it  requires less than 250MHz  clock frequency to compress H.264 in real-time.

The Hantro 8270 incorporates a proprietary indexed full search motion estimation algorithm to reduces clock requirement without affecting video quality. Built-in camera stabilization technologies further improve the quality and compression ratio of live video capture, and scene change detection algorithms improve transcode performance as well as bring significant benefits to surveillance solutions. 

Minimal power consumption, optimal silicon utilization and easy integration:

  • Optimize silicon area by selecting only the formats and functions needed.
  • Choose internal memory requirement according to your resolution requirements.
  • Share internal memories with the Hantro 8190 decoder for a full codec solution.
  • Choose bus protocol interfaces from AHB, AXI, OCP & APB.
  • Simple API. OpenMax, Symbian MDF and DirectShow® options available.

Supported formats and resolutions 

Format

ResolutionProfile
H.2641080p
High, Main & Baseline
JPEG16MpixelsBaseline DCT (sequential) & JFIF 1.02 file format


Hantro 8270 H.264 / JPEG  Encoder Block Diagram

 

Proprietary Video Stabilization  Technology 

The Hantro 8270 H.264 / JPEG Encoder incorporates unique technology to improve the observed image quality of captured video by counteracting the effects of camera shake. When the feature is enables, each frame or raw video is analyzed and the undesired movement is removed by cropping and repositioning the frame (illustrated below). The level of stabilization can be configured by defining the size of area to be cropped.

In addition to improving perceived image quality, compression efficiency is also increase as the frame analysis and cropping are done prior to encoding.

Hantro 8270 H264 / JPEG Encoder Deliverables
  • RTL source code (VHDL or Verilog) with an RTL test bench and test data.
  • ANSI C source code for hardware drivers with software test bench and test data.
  • Technical documentation; hardware and software integration guides and application programming interface (API) manuals.



TI New DSP for H.264 at 1080p



Dallas TX — Texas Instruments (TI) has announced the TMS320DM365, the first low-cost DaVinci processor to support H.264 encoding at 1080p. In addition to the increased encoding power, the DM365 features an image signal processing (ISP) engine with face recognition and other intelligent video processing capabilities. The DM365 also includes new peripherals that can drive system cost down by as much as 25%.

The DM365 is optimized for video security applications by supporting 1080p H.264 at 10 fps. This profile provides the high resolution and low bit rates need for camera applications. The device also supports MPEG-4, MPEG-2, MJPEG and VC1 codecs. For example, it supports 1080p MPEG-4 at 24 fps and 720p MPEG-4 at 30 fps. These profiles make the DM365 suitable for applications such as multi-channel DVRs, digital signage, and personal media players.


Figure 1. The DM365. Items in yellow are new compared to the DM355

The Image Signal Processor (ISP) offers a variety of pre-processing capabilities including face detection, noise filtering, video stabilization, auto white balance, auto focus, auto exposure and edge enhancement. The face detection capability is particularly notable, as it enables innovative applications. In a digital signage application, for example, face recognition can be used to detect viewers and display relevant content. The ISP is also notable for its ability to compensate for optics problems. This feature allows designers to use low-quality, inexpensive optics.

Other DM365 features include:
  • ARM926EJ-S core running at either 270 MHz or 300 MHz
  • Peripherals including EMAC, USB 2.0 Phy, 16-bit DDR2, voice codecs, real time clock and three 10-bit DACs
  • Royalty-free, production-ready codec bundles (MP3, G.711, H.264, MPEG-4 and JPEG) and premium audio and video bundles (AAC, WMA and AEC, MPEG-2, VC1/WMV9)
The TMX320DM365 is sampling now and is priced at $37.85 (100 units). TI also offers the TMDXEVM365 evaluation module for $595. This board comes with a MontaVistaPro 5.0 Linux board support package (BSP). The board is scheduled to get Windows Embedded CE support and eSOL RTOS support in the second half of the year.

For more information, see www.ti.com/dm365processor.



HD Video encoding for H.264 surveillance Using Low-cost FPGA


Low-cost FPGAs are now making it possible to implement highperformance encoding systems on  a cost-effective and lowpower FPGA fabric. This enables systems with the right combination  of power, performance, and price-points to be built using well-understood FPGA fabric. This article first lays out the architecture advantages of FPGAs for low-cost, yet  high-performance video processing applications and then shows how these advantages translate into a real-world application in the rapidly expanding field of video surveillance systems.

This design approach enables the implementation of an advanced, high-performance video application on a low-cost FPGA fabric. Such implementations are critical to meet the cost and power constraints today’s video systems generally require. A complete working quad-channel surveillance system can  be implemented using only a single mid-range FPGA that can be a significant technology enabler  for this important growing market.

Wednesday, March 25, 2009

Why Cisco’s Buying Pure Digital for $605M

Stacey Higginbotham | Thursday, March 19, 2009 | 11:26 AM PT | 9 comments

mino_250x200_031809UPDATED: As expected, Cisco today said it would buy Pure Digital, the maker of the Flip handheld video camera, for $590 million in stock. The deal will move Cisco deeper in the consumer market and give it control of a device that produces video, which it hopes will drive the sale of its Internet routing and switching equipment. Pure Digital has raised $68 million in its seven-year history.

Cisco has recently announced products that will control video delivery from the content provider all the way down to the home consumer. With Pure Digital it can control the content flowing the other way — from the home to content aggregation sites like YouTube or personalized channels offered by cable and telco TV providers. More details coming soon. Update:

It’s easy to draw a line between the Flip camcorder and bandwidth consuming video that Cisco hopes to encourage in order to sell more networking gear. However, there are other factors at play. The Pure Digital acquisition brings Cisco deeper into the consumer home, a journey Cisco began with its acquisition of Linksys and its home routers, and continued with its acquisitions of set-top box maker Scientific Atlanta and entertainment networking company KISS in 2005.

If Cisco can integrate or transfer the dead-simple Flip software and camcorder into its Scientific Atlanta boxes, and tie the Flip camcorder to its Linksys router, it can offer PC-free telepresence to consumers. This combines Cisco’s hope of wresting control of the digital home from the PC and putting it in the networkwith its love of video conferencing.

Telepresence, even more than the 2 million Flip cameras out there shooting short videos, would drive the amount of video content on networks sky high. Cisco estimates that a good HD telepresence experience requires speeds of 24 Mbps and requires quality of service guarantees — both of which Cisco equipment could help ensure. Cisco has already indicated its plans to add $20 billion to its bottom line with a focus on video, and it has launched products around the what it calls the “medianet,” to deliver video from the content provider to the consumer. Driving content in the other direction — from the user back up to a content provider — also makes sense, and the Flip cameras offer Cisco control of the consumer video-producing endpoint.

Ned Hooper, senior VP of corporate development and consumer group, agrees that the purchase can be tied to telepresence, but he stressed that this buy signified Cisco’s ongoing transformation from a backend infrastructure provider to a company known for making the consumer device experience easier. He emphasized that the combination of the network and Flip cameras could allow a person’s video content to be viewed anywhere.

“Historically content is locked to a device, and is not open to move around,” Hooper said. This deal helps change that paradigm for video, in the same way Cisco is trying to do with music in its latest Linksys music router, announced earlier this year.

To help make moving content around the home and to the web easier, Cisco purchased Pure Networks last year for its software that helps network devices easily and is pushing the HNAP home networking protocol . Hooper said Cisco would integrate HNAP into the Flip camera and would add features to make it easy to operate the Flip on a network based on Cisco gear. Think about how Apple gear all works well together as an example of such integration.  However, Hooper stressed that HNAP was open for anyone to license, meaning Cisco isn’t pursuing a closed system.

So, while this takes Cisco into a new market and forces it to compete with consumer electronics makers like Sony, Cisco will likely tie the Flip camcorders back into the network in a way that drives both consumer-oriented Cisco purchases and the need for advanced Cisco gear on the carrier side.

http://gigaom.com/2009/03/19/cisco-to-buy-pure-digital-for-590m/

So, what's inside of Flip?

http://www.eetasia.com/ART_8800506225_499489_NP_3a343a51.HTM

On removing the covers, I was at once disappointed and amazed. The disappointment derives from the gadget-freak in me that loves to see a maze of springs, motors and actuators supported by a rats nest of wires and myriad, complex-looking ICs. That was definitely not the case. In fact, I was amazed that the camera simply comprises the 2.8cm-high lens, two mini connectors (for the USB and button-control interfaces) and a single processing board with the sensor, video processor and two memory ICs.

However, it's the choice of components, and the software that went into them, that gives the Flip Ultra its uniqueness and edge. At the heart of the system is the marriage of a Micron 1/4inch VGA CMOS sensor with a Zoran Coach 8M (ZR36460BGCF) image processor. According to John Furlan, vice president of engineering at Pure Digital, the Micron sensor (MT9V011D00STC) was chosen not just because he believes Micron makes high-quality sensors, but also because it had the right pixel size of 5.6┬Ám square that would give maximum performance across all light ranges, from bright to poor. It also has the necessary frame rate of 30-90fps, programmable gain via a two-wire interface, on-board 10bit ADC a 10bit parallel output.

This output feeds directly into the Zoran processor. It is here where much of Pure Digital's intellectual property resides. According to Furlan, the team chose to go with Zoran as they already had a history of working with the company for its one-time-use cameras. However, they chose the Coach 8 specifically because, "it's very integrated, with a high-quality image-processing pipeline, as well as high-quality image compression—ware, versus DSP—B," said Furlan. In addition, Zoran made the full image-processing pipleline available to Pure Digital so they could perform the configurability they wanted, while still achieving the full 30fps, even in low light.

Fast digital image processing
The frame rate brings up an interesting point and speaks well of the Coach 8's processing power. Typical still cameras take a second or more to process an image, so how does the Flip manage 30 in a second? According to Furlan, as discussed previously, the video resolution is 640x480, which translates to approximately 0.25Mpixels. "So, a camera that can process and store a 4Mpixel image in 1s can process a 0.25Mpixel image in 1/16 of a second." Also, typical digital still cameras can process multiple frames per second. "In the end, it's the speed of the underlying hardware that permits us to process a video frame 30x per second," he said.

Secret sauce? Exposure control algorithms
The configurability of the processor also allowed Furlan's team to implement proprietary algorithms and core intellectual property to overcome one of the main obstacles to smooth digital video: auto exposure control. Careful control of both sensor gain and exposure across the range of scenes with appropriate smoothing is mandatory to ensure the user doesn't see significant changes in exposure on a frame-by-frame basis. This control of exposure, gain and image processing over a range of lighting conditions is a detail that's often overlooked, said Furlan.

Digital still cameras don't have this issue, as it's one exposure, one shot, while more expensive digital camcorders have external sensors and electromechanical light control. But the Pure Digital team had to do this digitally.

The "Eureka" moment came with the development of proprietary damping algorithms to implement a non-linear response curve off stasis to give a smooth 'landing' quickly, without instability in the system. "For slow or little change, we keep the auto exposure stable or make very small changes which cannot easily be discerned by viewers," said Furlan. While the auto exposure has no impact on the underlying video frame rate, it does improve the perception that as the camera moves from one scene to the next, there were no significant jumps in brightness.

The end result is a digital camcorder experience for $150 that rivals that of camcorders in the $500- to $600-range.

Zoran Coach 12

http://money.cnn.com/news/newsfeeds/articles/marketwire/0478466.htm

The COACH 12 processor family members support stills, HD 720P and HD 1080P video capture. Other features include efficient H.264 high definition video codec with integrated HDMI interface and face tracking, which detects and tracks multiple faces simultaneously so that the photographer can focus and track a subject anywhere within the frame.

XUPV5-LX110T Development Board

http://www.xilinx.com/univ/xupv5-lx110t.htm

The XUPV505-LX110T is a feature-rich general purpose evaluation and development platform with on-board memory and industry standard connectivity interfaces. It features the Virtex-5 XC5VLX110T device.

It is also called ML509. Reference design can be found at

http://www.xilinx.com/univ/xupv5-lx110t-refdes.htm

The documentation is similar to ML 505. which are in 

http://china.xilinx.com/products/boards/ml505/docs.htm

The XUPV5-LX110T is a unified platform for teaching and research in disciplines such as

  • Digital Design
  • Embedded Systems
  • Digital Signal Processing and Communications
  • Computer Architecture
  • Operating Systems
  • Networking
  • Video and Image Processing
  • High Speed Serial I/O Transceivers

XUPV5-LX110T



Features

The XUPV5-LX110T Development System features:

  • Xilinx Virtex-5 XC5VLX110T FPGA
  • Two Xilinx XCF32P Platform Flash PROMs (32 Mbyte each) for storing large device configurations
  • Xilinx SystemACE Compact Flash configuration controller
  • 64-bit wide 256Mbyte DDR2 small outline DIMM (SODIMM) module compatible with EDK supported IP and software drivers
  • On-board 32-bit ZBT synchronous SRAM and Intel P30 StrataFlash
  • 10/100/1000 tri-speed Ethernet PHY supporting MII, GMII, RGMII, and SGMII interfaces
  • USB host and peripheral controllers
  • Programmable system clock generator
  • Stereo AC97 codec with line in, line out, headphone, microphone, and SPDIF digital audio jacks
  • RS-232 port, 16x2 character LCD, and many other I/O devices and ports
Development System Includes
  • XUPV5-LX110T board
  • 1GB Compact Flash card
  • 256 MB SODIMM module
  • SATA cable
  • Platform USB programming cable
  • DVI to VGA adapter
  • 6A power supply
 

Running demo programs on XUPV5-LX110T

http://papillon.is.tokushima-u.ac.jp/

Currently the board is used by UC Berkeley EECS150 Spring 2009.


Ordering Information
To order this development system, click here, $750.00 for Academic

Tuesday, March 24, 2009

What is your choice of FPGA Synthesis tool?


Result of 3/25/09

Synplify by Synplicity
31% (125 votes)
Leonardo-Spectrum/ Precision RTL by Mentor
8% (31 votes)
DC FPGA - Synopsys
3% (12 votes)
XST by Xilinx
36% (147 votes)
Quartus by Altera
19% (77 votes)
Other
4% (15 votes)
Total votes: 407

Here is a white paper regarding to FPGA Performance Benchmarking Methodology.

Novas Verdi Automated Debug System

http://www.springsoft.com/product/product_more.aspx?id=34B874C68776DD91

The Verdi™ Automated Debug System is an advanced solution for debugging digital designs that provides powerful technology to help you:

  • Comprehend complex and unfamiliar design behavior;
  • Automate difficult and tedious debug processes; and 
  • Unify diverse and complicated design environments.


Cut Debug Time in Half
The Verdi system lets you focus on tasks that add more value to your designs by cutting your debug time, typically by over 50%. These time savings are made possible by unique technology that:

  • Automates behavior tracing with its unique Behavior Analysis technology;
  • Extracts, isolates, and displays pertinent logic in flexible and powerful design views; and
  • Reveals the operation of and interaction between the design, assertions, and testbench.

VerdiVerdi_3.jpg
 

The unique behavior analysis technology of the Verdi system automates many time-consuming aspects of debug.  

 

Complete Debug System
The Verdi Automated Debug System is a superset of the Debussy Debug System and incorporates all of the technology and capabilities of its predecessor.  In addition, the Verdi system combines advanced debugging features with support for a broad range of languages and methodologies.

Core Features 
The Verdi system provides the following fundamental debug features:

  • Full-featured Waveform Viewer enables you to display and analyze activity over time
  • Powerful Waveform Comparison Engine allows you to isolate differences between Fast Signal Database (FSDB) files
  • Source Code Browser enables you to easily traverse between source code and hierarchy
  • Flexible schematics and block diagrams give you the ability to display logic and connectivity using familiar symbols
  • Intuitive bubble diagrams help you to reveal the operation of finite state machines

Advanced Features
The Verdi system also includes the following advanced debug features:

  • Automatic tracing of signal activity enables you to quickly trace activity across many clock cycles with powerful behavior analysis technology
  • Temporal flow views provide a combined display of time and structure to help you rapidly understand cause-and-effect relationships
  • Transaction-based debug with flexible transaction and message support for debugging and analyzing designs at higher levels of abstraction
  • Assertion-based debug with built-in support for assertions facilitates quick traversal from assertion failure to related design activity
  • SystemVerilog testbench debug with:
    • Specialized views that help you to understand your testbench code, including declaration-based hierarchy browsing and navigation, class inheritance and relationship comprehension, and tracing
    • Unique message logging capability, coupled with advanced visualization techniques, give you a complete picture of testbench activity and your verification environment
    • Full-featured interactive simulation control allows you to step through complex testbench code for more detailed analysis

Languages and Methodologies
The Verdi system supports the following languages and methodologies:

  • Design components described in Verilog, VHDL, and SystemVerilog
  • Automated testbench environments using SystemVerilog Testbench (SVTB)
  • Assertions using SystemVerilog Assertions (SVA)


Optimized Open Architecture and Unified Methodology
The Verdi Automated Debug System is designed so that you can take full advantage of your verification and debug methodology. The Verdi system is built on the open Novas Design Knowledge Architecture, which consists of compilers that extract relevant information into databases that are optimized for efficient debug.  The Verdi system also unifies your debug process by providing a single solution that operates seamlessly and consistently across multiple domains – verification tools, design/verification languages, and abstractions. This consistency reduces your learning curve and saves time as you move to new projects using different tools and languages, and allows you to further leverage your investment in the Verdi system even as your other tools and methodology evolve. 

The Novas Design Knowledge Architecture is comprised of the following:

  • Knowledge Engine Compilers extract design knowledge contained in HDL code, testbenches, and assertions
  • Knowledge Database(KDB) stores crucial design knowledge to facilitate debug and understanding of your design
  • Fast Signal Database (FSDB) captures and store results from simulators, emulators, and formal tools that produce time/value sequences
  • Application Programming Interfaces (APIs) provide open access to both databases and command-and-control mechanisms, enabling you to easily integrate the Verdi system with other verification tools and design environments.
Interoperability

The Novas open architecture allows for easy integration with both commercial and proprietary verification tools. Through an ever-expanding list of partners, the Verdi system provides you with a fully integrated, predictable environment with out-of-the-box support for a wide range of commonly used commercial tools, including:

  • Simulators
  • Emulators and accelerators
  • Model checkers and other formal analysis engines

Debug and Analysis Across Multiple Abstraction Levels

The Verdi system further unifies comprehension by allowing you to seamlessly debug throughout your methodology flow from System level to Gate-level verification.  The Verdi system provides additional support for verification and analysis at the implementation level with the nAnalyzer Design Implementation Analysis module.  The nAnalyzer module provides a single environment for analyzing troublesome design errors related to clocks, clock trees, and timing. 
 -------------------------------------------------------------------------------------------------------------- 
The Verdi Automated Debug System Saves You Time

The Verdi Automated Debug System is an award-winning debug system that cuts your debug time in half.  This robust and sophisticated system significantly reduces the time and effort required to comprehend the behavior of complex designs by eliminating tedious and manual tasks.  The Verdi system’s open architecture and extensive integration with popular commercial tools unify your verification environment for even greater efficiency.  With over 400 customers and 60 EDA partners, the Verdi system has become the industry’s de facto standard debugger.  Our customers tell us that the time they saved using the Verdi system has given them more time to add greater value to their designs, work on other job-related tasks, and enjoy more personal time.  At SpringSoft, our mission is to accelerate engineers.  The Verdi Automated Debug System is one way that SpringSoft is Accelerating Engineers. 

 

 

Realted File Download: SS_Verdi_Datasheet_E5_US.pdf

Novas Verdi™ Debug Modules

The Novas Verdi™ Debug Modules comprise a spectrum of fundamental tools for understanding the structure of designs. At the core of the Verdi™ modules is the Novas Design Knowledge Architecture and robust set of compilers, specialized databases and APIs. These form an open, highly scalable infrastructure that connects design and verification knowledge to help designers better understand complex design behavior.

  •  Knowledge Engine Compilers extract detailed knowledge of design structure from VHDL and VerilogHDL source code.
  • Knowledge Database (KDB) stores relevant information for access by analysis, tracing and visualization  tools;
  • Fast Signal Database (FSDB) stores and optimizes loading of results from verification tools;
  • Open APIs interface with all popular third-party verification tools for consistent view throughout entire development flow.

The Verdi waveform, source code, and schematic modules use design knowledge to help designers quickly locate, isolate, and resolve design problems. These modules are fully integrated using point-and-click and drag-and-drop techniques for seamless navigation between views and greater overall debug productivity.

Verdi nWave™ module is a complete waveform viewing tool that provides a comprehensive and intuitive view of design activity over time.

  • Locate and isolate logic related to particular transitions and values
  • View higher-level design structures such as assertions and transactions

Debussy Debug_image001.jpg

Verdi nTrace™ module is a sophisticated source code browser that automates tracing of connectivity and related elements throughout the design.

  • Navigate designs in the hierarchy display or HDL source code view 
  • Annotate source code with simulation results for easy viewing and analysis
  • Automatically find active drivers and loads for specific signal transitions and values

Debussy Debug_image002.jpg

Verdi nSchema™ module is a schematic visualization tool that intelligently generates hierarchical or flat diagrams from RTL and gate-level descriptions.

  • Highlight and correlate in schematic views the portions of code being analyzed
  • Automatically locate and analyze cause-and-effect relationships
  • Render specialized schematic displays for structures such as fan-in and fan-out cones

Debussy Debug_image003.jpg 

Wednesday, March 18, 2009

Xilinx Virtex-5 family Overview


The new Virtex-5 devices are the world's first FPGAs to be fabricated at the 65 nm technology node. These devices are based on a low-K dielectric process that reduces parasitic capacitance, enables faster switching speeds, and reduces heat dissipation. Their 12-layer metallization (11 copper layers and 1 aluminum layer) supports an advanced diagonal interconnect fabric. Their core voltage has been reduced to 1.0V, thereby reducing dynamic power consumption (the core voltage of Virtex-4 devices is 1.2V). Meanwhile, their second-generation triple-oxide technology dramatically reduces static power dissipation.

Overall, the new Virtex-5 family provides 65% more logic cells and 25% more input/outputs (I/Os) as compared to the preceding Virtex-4 generation of devices. At the same time, members of the Virtex-5 family are claimed to provide 30% higher performance, 35% lower dynamic power dissipation, and they consume 45% less silicon real estate as compared to their Virtex-4 counterparts.

All members of the Virtex-5 family are based on Xilinx's ASMBL (Advanced Silicon Modular Block) architecture. For each application domain – such as digital signal processing – Xilinx has determine the optimum mixture (ratio) of logic, memory, DSP slices, and so forth. Next, for each application domain, Xilinx create a suite of components, all based on the same "mix" but with a range of capacities. This suite is collectively referred to as a "platform". Based on this, Xilinx have announced four domain-optimized platforms as follows:

  • Virtex-5 LX: High performance logic (shipping now).
  • Virtex-5 LXT: High performance logic with serial connectivity (coming in the second half of 2006).
  • Virtex-5 SXT: High performance DSP with serial connectivity (coming in the second half of 2006).
  • Virtex-5 FXT: Embedded processing with serial connectivity (coming in the first half of 2007).

Virtex-5 devices are also based on Xilinx's new ExpressFabric technology, which features LUTs with 6 independent inputs for fewer logic levels, and a new diagonal interconnect architecture that facilitates shorter, faster routing. An overview of some of the more significant Virtex-5 architectural features are as follows:

6-Input lookup tables (LUTs)
The first FPGA to be presented to the market in 1985 – the XC2064 from Xilinx – contained 64 configurable logic blocks (CLBs), each of which boasted two 3-input lookup tables (LUTS). Subsequent generations moved to 4-input LUTs, because these offered a more optimal balance with regard to logic utilization and minimizing the number of logic levels in the context of designs of that era.

However, there has been a fundamental shift in the nature of designs over recent years. Today's designs often feature wide data paths, especially in the case of digital signal processing (DSP) applications. Implementing these designs using 4-input LUTs can require many levels of logic, thereby impacting performance. In order to address this issue, the ExpressFabric employed by the Virtex-5 family feature's LUTs with six independent inputs, which can significantly reduce the number of logic levels required to implement wide functions (Fig 1).


1. The Virtex-5 family features 6-input LUTs.

Each of these logical elements can be used as a true 6-input LUT or as two 5-input LUTs that share five of their inputs. In addition to containing four 6-input LUTs, a Virtex-5 slice also includes faster flip-flops to speed pipelined designs and an improved carry chain architecture to speed arithmetic operations. Overall, Virtex-5 family provides 65% more logic cells (330,000 LCs) as compared to their Virtex-4 counterparts.

Diagonal interconnect
The traditional way of implementing FPGA interconnect results in a complex pattern as to which CLBs can be reached from an initial CLB in 1, 2, 3, or more hops. Consider the central (red) CLB shown in Fig 2 for example; from this starting point, the CLBs in yellow can be reached in 1 hop, the CLBs in green can be reached in 2 hops, and the CLBs in blue can be reached in three hops.


2. Traditional Virtex-4 interconnect pattern.

Reaching CLBs outside the blue area will require more hops. Note especially the "holes" in the blue areas; reaching CLBs in these holes will also require more hops. This complex arrangement impacts speed and increases the complexity of synthesis, place, and route. In irder to address this issue, another ExpressFabric feature is a radically new form of diagonal interconnect that reaches more locations with fewer hops (Fig 3). This diagonally symmetric interconnect pattern is intended to improve both speed and predictability.


3. Diagonally symmetric Virtex-5 interconnect pattern.

The combination of the ExpressFabric's 6-input LUTs and diagonally symmetric interconnect pattern results in an average increase of logic performance of 30% over the previous Virtex-4 generation of devices, which equates to up to two speed-grades. 

Faster, higher-capacity RAM blocks with hard IP
The new block RAM Structures (with pipeline) featured in the Virtex-5 family have been increased to 32 Kbits in size, which is twice the size of those found in Virtex-4 components. In addition to offering a simple dual-port mode that can double the block RAM's bandwidth, these also contain additional hard IP in the form of FIFO logic and new 64-bit error checking and correction (ECC) logic (Fig 4). Implementing this logic as hard IP frees up other resources and minimizes dynamic power consumption.


4. The Virtex-5 family features up to 10 Mbits of 550 MHz block RAM.

As with all of the hard IP blocks in Virtex-5 devices, these block RAMs have been tuned for 550 MHz operation to provide higher on-chip memory bandwidth. If required, unused 18 Kbit sub-blocks can be turned off so as to minimize power consumption.

Faster, wider DSP functions
The Virtex-5 hard DSP slice – called the DSP48E – features a 25 × 18 bit multiplier (versus the 18 × 18 multiplier employed in Virtex-4 FPGAs). The increase to a 25 × 18 bit multiplier can lead to fewer cascaded stages, thereby resulting in higher overall performance and utilization (Fig 5).


4. The Virtex-5 family features DSP slices with 25 × 18 multipliers.
(This illustration is a simplification of the DSP48E's functionality)

Tuned for 550 MHz operation, these high-precision, high-performance, highly flexible slices can be configured for DSP, arithmetic, and logic functions, and they can also be cascaded for adder chain architectures. (Observe that the multiplier is followed by a 3-input 48-bit "adder" that also perform logical operations such as AND, OR, XOR, etc.) The DSP48E Slice has 40% lower power consumption as compared to implementing equivalent functions in Virtex-4 FPGAs (1.38mW/100 MHz at a 38 percent toggle rate).

Advanced clock management
Virtex-5 devices offer up to 18 clock elements for flexibility and differential global clocking for low skew and jitter. The new 550 MHz clock management tile (CMT) in the Virtex-5 features two digital clock managers (DCMs) and a phase-locked loop (PLL). The DCMs provide precise phase control for better design margin, while the PLL reduces reference clock jitter by more than two times. Depending on each design's unique requirements, the PLL can be configured before or after the DCMs.

High-speed I/O and new packaging technology
Virtex-5 devices offer up to 1,200 general-purpose input/output (GPIO) pins, which is around 25% more than the previous Virtex-4 generation of components. These pins provide 1.25 Gbps differential I/O and 800 Mbps single-ended I/O. Additionally, Virtex-5 devices feature second-generation ChipSync source-synchronous technology, which allows programmable delays to be applied to both inputs and outputs (the previous generation of ChipSync supported delays only on input pins).

As opposed to the highest pin-count Virtex-4 devices, whose 960 pins were presented as 15 banks of 64 pins, the 1,200 pins in Virtex-5 components are presented as 30 banks of 40 pins. These smaller banks offer more flexibility in terms of I/O placement. Furthermore, Virtex-5 packages employ a new second-generation Sparse Chevron packaging technology, which is claimed to minimize signal integrity (SI) issues such as cross-talk and also to ease the task of PCB layout.

Pricing and availability
SynplicityMentor Graphics, and Magma Design Automation all support the Virtex-5 design flow. Early access software for Virtex-5 FPGAs is available now, with general availability in June 2006.

Virtex-5 LX FPGA engineering samples are shipping now in the LX50, LX85 and LX110 densities, with the LX30, LX220, and LX330 to follow over the next six months. At customer production timeframes in 2008, the LX50 device will list for $149, the LX85 device will list for $279, and the LX110 device will list at $399, all in 1,000 unit volumes. These price points represent savings of more than 50 percent over offerings of other competitive 90-nm FPGAs.

For even further cost reductions, the Virtex-5 EasyPath program will be available at time of volume production beginning in 2007. For more information, visit the Xilinx website at www.xilinx.com

LX110:
17,280 slices
129 BRAMs
64 DSP

LUT 69120
FF676, FF1153, FF1760

http://www.xilinx.com/products/virtex5/index.htm

http://www.nuhorizons.com/xilinx/virtexFXT/MPM_28_V5_psm_table.pdf

ftp://ftp.ni.com/pub/devzone/pdf/tut_7440.pdf

Saturday, March 14, 2009

HD FPGA Development Boards


The Cyclone III FPGA Development Kit ($1,495)is RoHS compliant and features:
  • Cyclone III development board (see Figure 1)
    • Cyclone III EP3C120F780 FPGA
    • Embedded USB-Blaster™ circuitry (includes an Altera MAX® II CPLD) allowing download of FPGA configuration files via the flash device or the host computer
  • Memory
    • 256 Mbytes of dual-channel DDR2 SDRAM with ECC
    • 8 Mbytes of synchronous SRAM
    • 64 Mbytes of flash
  • Communication ports
    • 10/100/1000 Ethernet
    • USB 2.0
  • Power and analog devices from Linear Technology
  • Clocking
    • 50-MHz and 125-MHz on-board oscillators
    • SMA inputs/outputs
    • Inputs/outputs for the two HSMCs
    • Various buttons, switches, and indicators
  • Display
    • 128 x 64 graphics LCD
    • 2-line x 16-character LCD
  • Connectors
    • Two HSMCs
    • USB type B
  • Debug tools
    • Three HSMC debug cards (two loop-back and a debug header)
  • Cables and power/analog
    • 14-V–20-V DC input
    • On-board power measurement circuitry
    • 19.8 W per HSMC interface
    • Power cord with plug adapters (US, UK, EU)
  • Cyclone III FPGA Development Kit, CD-ROM (download all CD contents via FTP)
    • Design examples for the Cyclone III FPGA development board
    • Complete documentation (see Table 2)
      • User guide
      • Reference manual
      • Board schematic and layout
      • Bill of materials
      • Product and partner information
  • Altera Complete Design Suite DVD
    • Quartus® II design software
      • Subscription Edition (optional feature, available for purchase)
      • Web Edition (no charge, Windows only)
    • ModelSim®-Altera software 
      • Altera Edition (optional feature, available for purchase)
      • Web Edition (no charge, Windows only)
    • MegaCore® IP Library - OpenCore Plus evaluation
      • Includes Nios II processor (evaluation license)
    • Nios II Embedded Design Suite, Evaluation Edition (no charge)
    • DSP Builder (optional feature, available for purchase)
    • Video demos of Quartus II software and Nios II embedded processor

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Figure 1. Cyclone III FPGA Development Board

Figure 1. Cyclone III FPGA Development Board



Features
  • Altera EP3C120F780 Development board
  • Bitec HSMC Quad Video daughter card
    • 8 composite or 4 s-video inputs
    • 1 HD (1080p) DVI Output port or
    • 1 TV (PAL/NTSC) output with resolutions to 1024x768 and support for composite, s-video or SCART (RGB) outputs
  • Bitec HSMC DVI daughter card
    • 1 HD (1080p) DVI Output port (HDMI with external adaptor)
    • 1 HD (1080p) DVI Input port (HDMI with external adaptor)
  • Interfaces directly to the Altera Video and Image Processing (VIP) Suit
  • Collection of video reference designs

Cyclone III Video Dev Kit

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